According to the website it's 3 seperate chips, each dual core. I see a few issues with this.
1) Parallel processing isn't well done yet. Programming methodology (do this, then this, then this) make it hard, and overhead is a pain. It'll be alot easier for a console since it's a set number of processors, where I assume the programmers would hardcode which processor they want to do what, but it still has drawbacks.
2) One shared L2 cache of 1MB. You're essentially splitting that into 3 smaller caches. And since this is a multi-chip implementation, it means the L2 cache will no longer be right next to the cores (current PC CPUs have L2 cache on the chip itself, right next to the core). That brings extra latency. This could be alot worse depending on which cache implementation they use. If they use the same as Intel (duplicate L1 cache, almost no overhead), then you're left with only 832KB of effective L2 cache. They can take the same approach as AMD, where nothing is duplicated, that just adds overhead because you're swapping back and forth.
3) There's only 64KB L1 cache per chip. Typical processors have 128KB L1 cache. With a dual core implementation, this makes it a potential killer of a bottleneck. All that extra MHz could show very little benefit, which brings me to my next point.
4) The MHz rating seems to be, well, optimistic. To put it mildly.
5) 65nm. Great in theory. However, I have two questions. One, as recently pointed out in an Ars Technica news topic, signal integrity is becoming a problem. You can't maximize the chip speed until you make sure there's no leaky signals. Also, what's the yield? Getting a few chips for samples is alot easier than mass producing.
So it all sounds great in theory, but how's it really going? I want the whole story.
