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AKA snkmad
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yes, it can be changed.
But you would have to re-program it to do it....
 

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I don't think it is a 'either-or' situation. In the future there may be AMD optimized(3D Now! is an AMD instruction set, or at least 3D Now! professional) builds of pcsx2, but by the future I mean(most likely, unless the devs have other plans) probably when the project 'matures'(ie.. full speed and most games working) and that probably wont be for a few more years. A better question would be if there is any plan to optimize the emulator for SSE3 which both Intel and AMD are introducing in their new chips(Dothan and Venice).

Edit: I forgot to mention that a program could have optimizations for both 3D Now! and SSE(in fact most do).
 

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Indeed SSE3 would be great,but the authors would need processors that have it,which will cost pretty much when they're out.
Also i think 3dnow is at the bottom of the optimisation list since you dont have any chance of even remotely achieving playable speeds with ps2 emulation using any athlon xp.
 

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bositman said:
Indeed SSE3 would be great,but the authors would need processors that have it,which will cost pretty mcuh when their out.
Also i think 3dnow is at the bottom of the optimisation list since you dont have any chance of even remotely achieving playable speeds with ps2 emulation using any athlon xp.
Ah! they will get cheaper after time, 2 or 3 years from now most people will probably have SSE3 along with less desireable things like TCPA.
 

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SSE2/3 are far more efficient FP SIMD extensions than any 3DNow! iteration, and much easier to write code around.. seeing how AMD gets support for Intel's latest SSE versions in almost no time (A64 Venice has SSE3), this shouldn't be that big of a problem.
 

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I know this is going to sound retarted, but it seems like my Celeron supports SSE2. pcsx2 says my cpu supports it and I can use the VU rec without problems oO
 

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AKA snkmad
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Why it shouldnt?
 

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I've explained it to you countless times before.. Celerons have all the same instruction sets as the Pentiums they are derived from..
 

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Umm.. each Pentium from the PII up has a Celeron counterpart, which is derived from its respective Pentium. The Northwood/Prescott Celerons are simply P4 Northwood/Prescotts with 1/4 the L2 Cache, and a lower FSB.. that's it.

They are derived from the P4. :hdbash:
 

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For a quick summary, here's a look at the major changes inside the Prescott core:

* 90nm Strained Silicon Process - more, faster transistors in less space
* 31 Pipeline Stages - for clock speed ramping
* Improved Branch Predictor - helps avoid pipeline stall
* Improved Scheduler - helps avoid doing unnecessary work
* Improved Execution Core - added integer multiply and fast shift to ALU
* Larger, Slower Caches - higher latency caches for speed and size scaling
* SSE3 - 13 new instructions
http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2093

it's all in anandtech site, if it as sse3, it has sse2!
 
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