Hey, I've been looking for a datasheet or some other type of documentation on the MIPS R5000 CPU. I've searched Google and IIRC the MIPS website and still never found one. Any ideas? Thanks.
Hope that helps..The R5000 is a 64 bit superscalar pipelined microprocessor which was released by MIPS in 1996, it has 64KB L1 cache split equally between instruction and data and processors were available with upto 1MB of L2 cache (theoretically 2MB could be used but wasn't implemented) or as little as none (in the case of the R5000PC 150).
The R5000 was the lower cost counterpart to the R10000, it has 2 pipelines as opposed to the 4 of the R10000, the bus to the L2 cache has been cut down from 128 bits to 64 bits, it can't execute instructions speculatively or out of order.
First released as an option on SGI Indy's the CPU was later used in the initially available (lower end) SGI O2's. It uses the MIPS IV instruction set, has 32fp/32int registers, each 64 bits wide and executes from a five stage pipeline.
The R5000 is optimised for single precision multiply-add FP operations, often used in 3D geometry calculations.
The processor was available in clock speeds between 150MHZ and 200MHZ (yes, really, an entire CPU line with only 3 (150, 180, 200) different clock speeds).
The RM5200 was introduced in 1999. Designed in a joint effort by MIPS and Quantum Effect Devices Inc as, essentially, a die shrunk up-clocked version of the R5000, it is/was available from SGI as an upgrade for R5000 O2's. Sadly when released it cost "as much as an aircraft carrier", specifically $1,495 as a trade-in, and no-one was going to buy a 300MHZ chip for $1500 in mid-late 1999.
The first link is an architecture design of R5000 in PDF format.. from mips site.i think he was asking about a design/chip register sheet or something like that....