A more correct ARM9 bios interrupt routine is used, avoiding the hack that I put in place previously where one of the registers loads was hard coded in the ARM9 evaluator.
The interrupt waiting SWI routine was using an incorrect register so the return from the wait was not reliable.
Bugs related to switching between ARM and Thumb mode, and restoration of the spsr from the cpsr at the end of an interrupt were fixed.
The interrupt handler expected the handler to be ARM code not Thumb code. The libnds handler is in Thumb so fixed code that was previously there but not working to execute Thumb code if the code is indeed thumb.
Implemented some of the ARM9 Coprocessor instructions for DTCM and ITCM handling (specifically registers 6 and 9).