CISC & RISC
Technically on the outside of the processor we can treat the x86 architecture as a CISC system, but on the inside in newer generations to get more speed it is actually breaking down the macro-operations into micro-ops which are each executed in one CPU cycle. They call this the "EPIC" style architecture, and is essentially a RISC style execution core with a CISC outside wrapper. This allows assemblers to create x86 machine code out of any object code from a programming language compiler and maintain compatibility across the new Pentium 4 line as well as the older CPUs. I believe AMD has a similar but slightly different approach.
Anyway, I'm not an expert but that's what I understood from someone else talking about it...